109 Configurable SR
109 : Configurable SR
- Author: Greg Steiert
- Description: Configurable gates driving SR and D flip-flops
- GitHub repository
- Clock: 0 Hz
How it works
Two configurable gates enable a variety of complex flip-flop functions
How to test
When SEL and INV are low, the 0 inputs directly drive the flip-flops. A-0 can be connected to the clock for use with the D flip-flop.
External hardware
none
IO
| # | Input | Output |
|---|---|---|
| 0 | A-0 | MUX-A |
| 1 | A-1 | XOR-A |
| 2 | A-SEL | SR-Q |
| 3 | A-INV | D-Q |
| 4 | B-0 | MUX-B |
| 5 | B-1 | XOR-B |
| 6 | B-SEL | SR-Q# |
| 7 | B-INV | D-Q# |