This design implements three different ring oscillators. The first one is a basic NAND based oscillator. The second one adds additional NAND gates to the outputs of the stages of the oscillator to increase the capacitve loading. The last one uses the tri-state inverts with a sub-threshold tri-state enable.
For measuring the frequencies each oscillator is driving a counter. This counters are latched with the latch counter input. With the input transfer counter the currently selected counter (counter select bits) is transfered via the serial data stream. The transfer is driven by the clock of the design. As encoding a manchester encoding is used.
Furthermore, a divided version of the clock of each oscillator is outputted. The divisior can be configured with the frequency selection bits.
TODO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | latch counter | ||
| 1 | counter reset | ||
| 2 | transfer counter | ||
| 3 | counter select bit 0 | ||
| 4 | counter select bit 1 | serial data stream | |
| 5 | select latch counter (sync/async) | divided clock of oscillator 0 | |
| 6 | frequency divider select bit 0 | divided clock of oscillator 1 | |
| 7 | frequency divider select bit 1 | divided clock of oscillator 2 |