This text will be updated nearer the scheduled TT05 redistribution time (early 2024) along with the project github README.md and gh-pages documentation. Please regenerate your documentation.
Issue synchronous reset, ensure interface inputs are set to zero. Power-on-reset configuration is possible via the input pins, see documentation.
This design is an I2C peripheral that implements an 8-bit ALU over I2C. The purpose of the ALU is to allow pattern testing to occur and read back the accumulated result.
There are a few clocking modes, the default uses SCL pin as per the standard.
Connection to I2C interface:
When in open-drain mode the standard pull-up resistor is in the order of 4k7 to 10k and no more than 400pF capacitance on lines. Higher speeds my require attention to those metrics for your setup. The project is peripheral only and does not drive SCL. So open-drain or push-pull can be used by the controller no matter the mode setup in this project.
Power-on-reset configuration (set all zero for standard mode):
The design is based around a high-speed clock, at default speed of 10MHz with
Other than the default divider setup for CLOCKMUX mode there is no restriction upon the system clock used, other than trying to operate at low ratios of system-clock:SCL. The design has been simulated from "6:1" upto 1000000:1. Maybe lower than 6:1 are possible.
RP2040 code is expected to be provided to conduct testing based on simulation expectations.
I2C Controller/RP2040
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | i2cSampleDivisor bit0 | segment a | |
| 1 | i2cSampleDivisor bit1 | segment b | |
| 2 | segment c | I2C SCL (bidi) | |
| 3 | segment d | I2C SDA (bidi) | |
| 4 | segment e | ||
| 5 | segment f | ||
| 6 | segment g | ||
| 7 | dot | powerOnSense (out) |